1. Field of the Invention
The present invention relates to a memory controller for driving liquid crystal display devices, and, in particular, to a controller that achieves better memory utilization while simultaneously reducing the multiplex ratio of programmable multiplex ratio solutions of the memory device.
2. Description of the Related Art
In driving a liquid crystal display (LCD), a multiplex method is typically used where the display dots of the LCD are divided into a number of groups. Each group is provided with a common electrode, which is usually a row electrode. The common electrodes are sequentially selected to drive the dots of the group, thereby producing a pattern on the LCD. By using this multiplex method, problems with driving large LCDs are avoided, such as layout pattern limitations, among others.
A typical pulse waveform is illustrated in FIG. 1, which shows a driving pulse for eight rows, R0-R7. In a time period T0, for a mux M0, a pulse is sent to row R0, followed by a pulse sent to R1, etc., until all of the rows have been sequentially pulsed. The Mux M0/2 has a period twice as long as that of M0, and consequently, only the four rows, R0-R3 are strobed.
A typical LCD 10 is shown in FIG. 2 and comprises the following components. A RAM memory 12 is comprised of a number of memory cells, and stores data ultimately written to a display screen 30. The memory 12 is supplied by an interface logic 14, which itself receives instructions from a set of programming inputs. The interface logic 14 also provides signals to a control logic component 16, which has another input from a timing generator 18, itself receiving an input from an oscillator input.
Data from the memory 12 is presented to a series of NC data latches 20, where NC represents the number of columns displayed by the standard LCD display unit. Coupled to the set of data latches 20 is a set of shift registers 22, which also receives signals from the control logic 16. The set of shift registers 22 is NR bits wide, where NR indicates the number of rows in the standard LCD display unit.
Output from the data latches 20 is fed to a column driver circuit 24, and output from the shift registers 22 is fed to a row driver circuit 26. The row driver circuit 26 also receives a signal from the control logic 16. There are NC separate column drivers in the column driver circuit 24 and NR separate row drivers in the row driver circuit 26.
The column outputs from the column driver 24 and the row outputs from the row driver circuit 26 are sent to an LCD display unit 30 for display. These column and row outputs are the interface between the LCD 10 and the LCD display unit 30.
Shown in FIG. 3 is a graphical representation of the column driver circuit 24 and the row driver circuit 26. The row driver circuit 26 is shown at the top of the figure, while the column driver circuit 24 is shown at the bottom of the figure. A representation of the memory 12 resides in the middle portion of FIG. 3. The LDC display unit 30 has hundreds or thousands of dots, each dot energized or not depending on data located at a junction of one of the NR lines (rows) and one of the NC bits (columns).
Sometimes the size of the memory is determined by the maximum column size needed and the maximum number of rows needed. Occasionally, the user was forced to modify the size of the memory by the number of contact pads that were available on the chip, oftentimes leaving portions of the memory unused.
In many prior LCD controllers a feature is present that enables a programmable multiplex ratio in order to address many different LCD display types. Multiplex ratio modification affects the LCD controllers in several ways.
First, modifying the multiplex ratio requires that the voltage levels be adapted in order to guarantee optimum optical contrast at the minimum energy absorption. This reduces the overall power requirements of the LCD controllers because the voltage can be optimized so that a minimum of less energy is absorbed by the LCD display screen.
Second, the number of voltage pulses generated during the time of one frame, which is the time period needed to completely refresh all of the display rows, must be adapted accordingly. This preserves a quality image displayed on the LCD display.
Third, the time slice devoted to a single row increases linearly with the multiplex ratio reduction, and in an opposite way, decreases linearly with an increase in the multiplex ratio. This can be seen in reference to FIG. 1.
Fourth, if the multiplex ratio is reduced, fewer rows of the LCD display are used (also seen in FIG. 1) and the memory used to support more rows than are being used becomes partially unused.
The last point is measured by a relationship comparing memory that is used to a total amount of available memory:(used memory)/(available memory)  (1)
As the multiplex ratio decreases, the amount of memory that is unused increases. Therefore, the above relation is reduced.
Alternatively, applications are sometimes required to combine a small number of rows (low multiplexing factor), thereby creating a large number of columns.
Prior LCD controllers, in an effort to provide flexibility for several multiplexing options, provided an amount of memory that is as large or larger than would be necessary for driving the display in any possible row/column configuration.
For example, as seen in FIG. 4, for a display having NC column drivers and NR row drivers, a memory 32 having NC1>NC bits per row may be used. The memory 32 of FIG. 4 is similar to the memory 12 shown in FIGS. 2 and 3, but has a larger number of columns per row. In this case, some of the row drivers could be converted into column drivers. Having more bits per row would increase the number of column drivers needed due to the increase in the size of the rows, while decreasing the number of row drivers needed, because with larger rows, fewer rows are needed for a given size memory. Therefore, some of the drivers that are normally used to drive rows can be converted into column drivers. With reference to FIG. 4, the number of row drivers 26a that are still used to drive rows in the row driving circuit 26, after conversion would be NR−(NC1−NC). The number of column drivers 26b in the “row” driving circuit 26 would be (NC1−NC), with one-half this amount being present on each side of the row drivers 26a. 
A problem with the above scheme of the prior art is that the ratio in equation (1) will always be less than unity, and oftentimes much less.
An additional problem with the above scheme is that a different sized memory is used, that is the memory 32 has NC1 bits per row while the memory 12 has NC bits per row. It would be desirable to use a standard size memory for all different types of LCD controllers, rather than having to customize the memory for each display type.
The technical problem solved by the present invention is to provide a configurable, flexible LCD controller adaptable to a wide variety of multiplexing ratios while at the same time maximizing the use of available memory.